A. D. Pimentel | PCS group

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The paper 'Revisiting Edge AI: Opportunities and Challenges' was published in IEEE Internet Computing.
FAA+RTS: Designing Fault-Aware Adaptive Real-Time Systems - From Specification to Execution
Postpandemic Conferences: The DATE 2023 Experience
Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation
Automated Exploration and Implementation of Distributed CNN Inference at the Edge
3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems
Building a Fine-Grained Analytical Performance Model for Complex Scientific Simulations
Embedded computersystemen explOratie
Exploring Multi-core Systems with Lifetime Reliability and Power Consumption Trade-offs
FLORIA: A Fast and Featherlight Approach for Predicting Cache Performance
GCN-based reinforcement learning approach for scheduling DAG applications
Hierarchical Design Space Exploration for Distributed CNN Inference at the Edge
Lifetime Estimation for Core-Failure Resilient Multi-Core Processors
PELSI: Power-Efficient Layer-Switched Inference
Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations
CPU-GPU Layer-Switched Low Latency CNN Inference
Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Model-Based Testing of Internet of Things Protocols
AutoDiCE (Automated Distributed CNN Inference at the Edge)
Modelling Performance Loss due to Thread Imbalance in Stochastic Variable-Length SIMT Workloads
TCPS: A Task and Cache-aware Partitioned Scheduler for Hard Real-time Multi-core Systems
Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core Systems
Improving the Robustness of Industrial Cyber-Physical Systems through Machine Learning-Based Performance Anomaly Identification
Methodologies for Design Space Exploration
Scenario Based Run-time Switching for Adaptive CNN-based Applications at the Edge
Power management for multicore processors
T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core Processors
Exploring Cell-based Neural Architectures for Embedded Systems
Power passports for fault tolerance: Anomaly detection in industrial CPS using electrical EFB
The Choice of AI Matters: Alternative Machine Learning Approaches for CPS Anomalies
An Analytics-Based Method for Performance Anomaly Classification in Cyber-Physical Systems
Software Passports for Automated Performance Anomaly Detection of Cyber-Physical Systems
ALOHA: an architectural-aware framework for deep learning at the edge
Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project
On the Effectiveness of Communication-Centric Modelling of Complex Embedded Systems
Work-in-Progress: Communication-Centric Analysis of Complex Embedded Computing Systems
Run-time Mapping Algorithm for Dynamic Workloads using Process Merging Transformations
SysRT: A Modular Multiprocessor RTOS Simulator for Early Design Space Exploration
Run-time Resource Allocation for MPSoCs using Tree-based Design Space Exploration
Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration
EDiFy: An Execution time Distribution Finder
A hierarchical run-time adaptive resource allocation framework for large-scale MPSoC systems
Scenario-based Run-time Adaptive MPSoC Systems
A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs
A Run-time Self-adaptive Resource Allocation Framework for MPSoC Systems
Fast and Precise Cache Performance Estimation for Out-Of-Order Execution
Towards Self-adaptive MPSoC Systems with Adaptivity Throttling
A System-level Simulation Framework for Evaluating Task Migration in MPSoCs
A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC
Emulating Asymmetric MPSoCs on the Intel SCC Many-core Processor
Exploring Task Mappings on Heterogeneous MPSoCs using a Bias-Elitist Genetic Algorithm
Towards Exploring Vast MPSoC Mapping Design Spaces using a Bias-Elitist Evolutionary Approach
Using Chip Multithreading to Speed Up Scenario-Based Design Space Exploration: A Case Study
A Scenario-based Run-time Task Mapping Algorithm for MPSoCs
A System-level Infrastructure for Multi-dimensional MP-SoC Design Space Co-exploration
An Iterative Multi-Application Mapping Algorithm for Heterogeneous MPSoCs
Exploiting Domain Knowledge in System-level MPSoC Design Space Exploration
A high-level power model for MPSoC on FPGA
A signature-based power model for MPSoC on FPGA
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems
Design space pruning through hybrid analysis in system-level design space exploration
Evaluation of runtime task mapping using the rSesame framework
Interleaving methods for hybrid system-level MPSoC design space exploration
VMODEX: a novel visualization tool for rapid analysis of heuristic-based multi-objective design space exploration of heterogeneous MPSoC architectures
2011 International Conference on Embedded Computer Systems, Architectures, Modeling, and Simulation : IC-SAMOS 2011: July 18-21, 2011, Samos, Greece : proceedings
A high-level power model for MPSoC on FPGA
An interactive visualization tool for the analysis of multi-objective embedded systems design space exploration
Design metrics and visualization techniques for analyzing the performance of MOEAs in DSE
Techniques and visualization approaches for analyzing local and global Pareto optimal sets in Multi-Objective Design Space Exploration
A high-level microprocessor power modeling technique based on event signatures
A trace-based scenario database for high-level simulation of multimedia MP-SoCs
Evaluation of runtime task mapping heuristics with rSesame - a case study
NASA: A generic infrastructure for system-level MP-SoC design space exploration
Runtime task mapping based on hardware configuration reuse
Visualization of multi-objective design space exploration for embedded systems
VMODEX: A visualization tool for multi-objective design space exploration
2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2009): October 15-16, 2009, Grenoble, France
Electronic system-level synthesis methodologies
Introduction
rSesame - A generic system-level runtime simulation framework for reconfigurable architectures
Signature-based calibration of analytical performance models for system-level design space exploration
System-level MP-SoC design space exploration using tree visualization
System-level runtime mapping exploration of reconfigurable architectures
Visualization of computer architecture simulation data for system-level design space exploration
Calibration of abstract performance models for system-level design space exploration
Proceedings of the 2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-time Multimedia (ESTImedia 2008)
Signature-based calibration of analytical system-level performance models
System-level design space exploration of dynamic reconfigurable architectures
The Artemis workbench for system-level performance evaluation of embedded systems
Tool integration and interoperability challenges of a system-level design flow: A case study
Towards design space exploration for biological systems
Towards system level runtime design space exploration of reconfigurable architectures
A Framework for Rapid System-level Exploration, Synthesis, and Programming of Multimedia MP-SoCs
A Framework for System-level Modeling and Simulation of Embedded Systems Architectures
Evaluating the Design of Biological Cells using a Computer Workbench
Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration
Static Priority Scheduling of Event-Triggered Real-Time Embedded Systems
Taking the example of computer systems engineering for the analysis of biological cell systems
Towards Multi-application Workload Modeling in Sesame for System-level Design Space Exploration
A Microthreaded Architecture and its Compiler
A Mixed-level Co-simulation Method for System-level Design Space Exploration
Multiobjective Optimization and Evolutionary Algorithms for the Application Mapping Problem in Multiprocessor System-on-Chip Design
On the Calibration of Abstract Performance Models for System-level Design Space Exploration
Special Issue on Architectures, Modeling, and Simulation for Embedded Processors
A Case for Visualization-integrated System-level Design Space Exploration
A systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
Proceedings of the 5th International Workshop on Embedded Computer Systems: Architectures, Modeling asd Simulation
The Artemis Workbench for System-level Performance Evaluation of Embedded System Architectures at Multiple Abstraction Levels
A High-level Programming Paradigm for SystemC
A High-level Programming Paradigm for SystemC
On the Modeling of Intra-task Parallelism in Task-level Parallel Embedded Systems
Proceedings of the 3rd and 4th Int. Workshop on Systems, Architectures, MOdeling, and Simulation
Static Priority Scheduling of Event-Triggered Real-Time Embedded Systems
A Multiobjective Optimization Model for Exploring Multiprocessor Mappings of Process Networks
A Software Framework for Efficient Systemlevel Performance Evaluation of Embedded Systems
An IDF-based Trace Transformation Method for Communication Refinement
IDF Models for Trace Transformtions: A Case Study in Computational Refinement
Utilizing Synthesis Methods in Accurate Systemlevel Exploration of Heterogeneous Embedded Systems
Modeling Intra-task Parallelism in Task level Parallel Embedded Systems
Modeling of Intra-task Parallelism in Sesame
Towards Efficient Design Space Exploration of Heterogenious Embedded Media Systems
Exploring embedded-systems architectures with Artemis
Non-DMA I/O in Startemis
Performance evaluation of the LH*1h scalable, distributed data structure for a cluster of workstations
Rapid evaluationof instantiations of embedded systems architectures: A case study
Sesame: Simulation of embedded system architectures for multi-level exploration
The Artemis modelling and simulation workbench: status and challenges ahead
Towards efficient design space exploration of heterogeneous embedded media systems
Hardware versus Hybrid Data Prefetching in Multimedia Processors: A Case Study
LH*1h: Implementation on a Cluster of Workstations
On Hybrid Abstraction-level Models in Architecture Simulation
The (S)tartemis case study
The Artemis Architecture Workbench
Evaluation of LH*lh for a multicomputer architecture
Issues for mapping tasks to components in the architecture workbench. Artemis Report 2
On mutiple abstraction levels in an architecture workbench. Artemis Report 4
SESAME: Simulation of Embedded System Architectures for Multi-level Exploration. Artemis Report 1
TriMedia CPU64 architecture
A combined hardware/software solution for stream prefetching in multimedia applications
A Computer Architecture Workbench
Design issues for high performance simulation
Distributed simulation of multicomputer architecture with Mermaid
Proc. of the 11th int. parallel processing symposium
Scalar versus stream data prefetching for the Tri Media
Abstract workload modelling in computer architecture simulation
An architecture workbench for multicomputers
Distributed simulation of multicomputer architectures with Mermaid
Evaluation of hardware-based and hybrid prefetching techniques for the TM1
RAPID: RAPid Interpretation of Data
Runtime visualization of computer architecture simulations
Evaluation of a Mesh of Clos Wormhole Network
The Mermaid Architecture-workbench for Multicomputers
Mermaid: modelling and evaluation research in MIMD architecture design
Mermaid: modelling and evaluation research in MIMD architecture design
Mermaid: modelling and evaluation research in MIMD Architecture design
Mermaid: Modelling and Evaluation Research in mimd Architecture Design
Mermaid: Modelling and Evaluation Research in MIMD Architecture Design
Modelling and Evaluation Research in mimd Architecture Design (Mermaid)
Simulating mimd Multicomputers: the Mermaid approach
Simulation of a Mesh of Clos Wormhole Network