R. Piscitelli

Latest

• Pruning techniques for multi-objective system-level design space exploration
• A high-level power model for MPSoC on FPGA
• A signature-based power model for MPSoC on FPGA
• Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems
• Design space pruning through hybrid analysis in system-level design space exploration
• Interleaving methods for hybrid system-level MPSoC design space exploration
• A high-level power model for MPSoC on FPGA