Embedded multicore systems are often built for a specific application, operating a combination of homogeneous and heterogeneous cores. These devices are often deployed for a long term and therefore system lifetime reliability is an important consideration while designing them. In principle, placing extra cores increases the lifetime reliability albeit at the cost of increased power consumption and chip area. We propose a framework to explore platform architectures and their floorplans, highlighting the trade-offs between lifetime reliability and power consumption. The framework is based on a Genetic Algorithm and employs a high level simulator to calculate the Mean Time to Failure (MTTF) of the chip. The simulator runs multiple times, also called Monte Carlo simulation, to take the averages of both failure times and power usage. The high number of simulations required makes the framework compute intensive. We therefore propose two variations of the design space exploration to reduce the number of simulations. Our results show that total number of simulations is reduced by ≈ 30% and the total GA convergence time by ≈ 55%, while the resulting floorplan designs are similar in their characteristics across all exploration varieties.