Publications

(2019). Response time analysis of multiframe mixed-criticality systems. Proceedings of the 27th International Conference on Real-Time Networks and Systems, RTNS 2019.

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(2019). CPpf: A prefetch aware LLC partitioning approach. Proceedings of the 48th International Conference on Parallel Processing, ICPP 2019.

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(2019). Software Passports for Automated Performance Anomaly Detection of Cyber-Physical Systems. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. SAMOS 2019.

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(2018). On the Effectiveness of Communication-Centric Modelling of Complex Embedded Systems. 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2018).

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(2017). SysRT: A Modular Multiprocessor RTOS Simulator for Early Design Space Exploration. Proc. of the 17th Int. Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS ‘17).

(2017). Run-time Mapping Algorithm for Dynamic Workloads using Process Merging Transformations. Proc. of the 17th Int. Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS ‘17).

(2017). Run-time Resource Allocation for MPSoCs using Tree-based Design Space Exploration. Proc. of the 12th Int. Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’17).

(2017). Scenario-Based Design Space Exploration. Handbook of Hardware/Software Codesign.

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(2017). EDiFy: An Execution time Distribution Finder. 2017 54th ACM EDAC IEEE Design Automation Conference (DAC 2017).

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(2016). Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study. Proceedings, IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.

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(2016). Scenario-based Run-time Adaptive MPSoC Systems. Journal of Systems Architecture.

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(2016). Improving Voltage Control in MV Smart Grids. 2016 IEEE International Conference on Smart Grid Communications (SmartGridComm).

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(2016). A tool for bottleneck analysis and performance prediction for GPU-accelerated applications. 2016 IEEE 30th International Parallel and Distributed Processing Symposium Workshops : IPDPSW 2016.

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(2015). Towards Self-adaptive MPSoC Systems with Adaptivity Throttling. Proceedings: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XV): July 20-23, 2015, Samos, Greece.

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(2015). Fast and Precise Cache Performance Estimation for Out-Of-Order Execution. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE): 9-13 March 2015, Grenoble, France.

(2015). A Run-time Self-adaptive Resource Allocation Framework for MPSoC Systems. 2015 European Conference on Circuit Theory and Design (ECCTD): August 24-26, 2015, Trondheim, Norway.

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(2015). A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs. ACM Transactions on Embedded Computing Systems.

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(2014). Using Chip Multithreading to Speed Up Scenario-Based Design Space Exploration: A Case Study. RAPIDO’14: proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools: 22 January, 2014, Vienna, Austria.

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(2014). Towards Hybrid Array Types in SAC. CEUR Workshop Proceedings.

(2014). Towards Exploring Vast MPSoC Mapping Design Spaces using a Bias-Elitist Evolutionary Approach. 2014 17th Euromicro Conference on Digital System Design: DSD 2014: proceedings: 27-29 August 2014, Verona, Italy.

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(2014). Smart Cyber Infrastructure for Big Data processing. Optical Fiber Communications Conference and Exhibition : OFC 2014.

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(2014). Optimizing a calibration software for radio astronomy. Proceedings, 16th IEEE International Conference on High Performance Computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014, 6th International Symposium on Cyberspace Safety and Security, CSS 2014.

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(2014). Next Generation Asynchronous Adaptive Specialization for Data-Parallel Functional Array Processing in SAC: Accelerating the Availability of Specialized High Performance Code. Implementation and Application of Functional Languages: 25th International Symposium, IFL 2013: Nijmegen, The Netherlands, 28-30 Augustus, 2013: revised selected papers.

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(2014). Emulating Asymmetric MPSoCs on the Intel SCC Many-core Processor. 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing: proceedings: PDP 2014: 12-14 February 2014, Turin, Italy.

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(2014). Active Resource Management for Declarative Data-Flow Processing. Preproceedings of the 15th Symposium on Trends in Functional Programming (TFP2014).

(2014). A System-level Simulation Framework for Evaluating Task Migration in MPSoCs. CASES ‘14: proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems.

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(2014). A Case Study in Coordination Programming: Performance Evaluation of S-Net vs Intel's Concurrent Collections. Proceedings: 2014 IEEE 28th International Parallel and Distributed Processing Symposium Workshops: IPDPSW 2014: 19-23 May 2014, Phoenix, Arizona.

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(2013). User-Defined Shape Constraints in SAC. The 25th Symposium on Implementation and Application of Functional Languages (IFL 2013).

(2013). Towards Persistent and Parallel Asynchronous Adaptive Specialisation for Data-Parallel Array Processing in SAC. The 25th Symposium on Implementation and Application of Functional Languages (IFL 2013).

(2013). Task Migration for S-Net/LPEL. FD-COMA 2013: 2nd HiPEAC Workshop on Feedback-Directed Compiler Optimization for Multi-Core Architectures: 8th International Conference on High-Performance and Embedded Architectures and Compilers: HIPEAC 2013: Berlin, Germany, January 21-23, 2013.

(2013). Statistical Performance Analysis of an Ant-Colony Optimisation Application in S-Net. FD-COMA 2013: 2nd HiPEAC Workshop on Feedback-Directed Compiler Optimization for Multi-Core Architectures: 8th International Conference on High-Performance and Embedded Architectures and Compilers: HIPEAC 2013: Berlin, Germany, January 21-23, 2013.

(2013). Persistent Asynchronous Adaptive Specialisation for Data-Parallel Array Processing in SAC. CPC2013: 17th Workshop on Compilers for Parallel Computing: July 3-5, 2013, Lyon. Program.

(2013). Fitness Prediction Techniques for Scenario-based Design Space Exploration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

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(2013). Dynamic Optimization of SLA-Based Services Scaling Rules. Proceedings IEEE 5th International Conference on Cloud Computing Technology and Science.

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(2013). An Efficient Scalable Runtime System for S-Net Dataflow Component Coordination. Programmiersprachen und Grundlagen der Programmierung, 17.Kolloquium, KPS 2013, Wittenberg, Germany.

(2013). A Scenario-based Run-time Task Mapping Algorithm for MPSoCs. Proceedings of the 50th Annual Design Automation Conference (DAC ‘13).

(2013). A Data-Flow Based Coordination Approach to Concurrent Software Engineering. 2012 Second Workshop on Data-Flow Execution Models for Extreme Scale Computing: DFM 2012. Proceedings.

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(2012). AstroHPC'12 foreword. Astro-HPC ‘12 - Workshop on High-Performance Computing for Astronomy.

(2012). A4MMC foreword. Lecture Notes in Computer Science.

(2012). User-Defined Shape Constraints in SAC. Draft proceedings of the 24th Symposium on Implementation and Application of Functional Languages (IFL 2012).

(2012). Single Assignment C (SAC): High Productivity meets High Performance. Central European Functional Programming School.

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(2012). SAC on a Niagara T3-4 server: lessons and experiences. Applications, tools and techniques on the road to exascale computing.

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(2012). SAC on a Niagara T3-4 Server: Lessons and Experiences. Advances in Parallel Computing.

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(2012). Radio astronomy beam forming on many-core architectures. Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium : IPDPS 2012.

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(2012). Modeling Streams-based Variants of Ant Colony Optimisation for Parallel Systems: a Dataflow-driven Approach Using S-Net. FD-COMA 2012: Workshop on Feedback-Directed Compiler Optimization for Multicore Architectures: 7th International Conference on High-Performance and Embedded Architectures and Compilers: HIPEAC 2012: Paris, France, January 25, 2012.

(2012). Lazy reference counting for the Microgrid. 2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT): 25 February 2012, New Orleans, USA: proceedings.

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(2012). Interleaving methods for hybrid system-level MPSoC design space exploration. 2012 International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation: proceedings: IC-SAMOS 2012, July 16-19, 2012, Samos, Greece.

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(2012). Fast scenario-based design space exploration using feature selection. ARCS 2012 Workshops: 28. Februar - 2. März 2012: München, Germany. Proceedings.

(2012). Distributed S-Net: Cluster and Grid Computing without the Hassle. Proceedings: 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing: Ottawa, Canada, 13-16 May 2012.

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(2012). Design space pruning through hybrid analysis in system-level design space exploration. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012.

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(2012). Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation: proceedings: IC-SAMOS 2012, July 16-19, 2012: Samos, Greece.

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(2012). An infrastructure for multi-level optimisation through property annotation and aggregation. NFPinDSML’12: Proceedings of the Fourth International Workshop on Nonfunctional System Properties in Domain Specific Modeling Languages.

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(2012). A SAFE approach towards early design space exploration of Fault-tolerant multimedia MPSoCs. CODES+ISSS ‘12: Proceedings of the eigth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis.

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(2012). A high-level power model for MPSoC on FPGA. IEEE Computer Architecture Letters.

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(2011). Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?. Proc. of the 9th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia ‘11).

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(2011). Towards an effective unified programming model for many-cores. 2011 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2011.

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(2011). The essence of synchronisation in asynchronous data flow. 25th IEEE International Parallel and Distributed Processing Symposium (IPDPS’11).

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(2011). Techniques and visualization approaches for analyzing local and global Pareto optimal sets in Multi-Objective Design Space Exploration. Workshop proceedings - 24th International Conference on Architecture of Computing Systems, ARCS 2011.

(2011). On mapping distributed S-Net to the 48-core Intel SCC processor. 3rd Many-core Applications Research Community (MARC) Symposium.

(2011). Implementation architecture and multithreaded runtime system of S-Net. Implementation and Application of Functional Languages.

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(2011). Efficient memory copy operations on the 48-core Intel SCC processor. 3rd Many-core Applications Research Community (MARC) Symposium.

(2011). Design metrics and visualization techniques for analyzing the performance of MOEAs in DSE. 2011 International Conference on Embedded Computer Systems, Architectures, Modeling, and Simulation : IC-SAMOS 2011.

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(2011). Descriptor-free representation of arrays with dependent types. Implementation and Application of Functional Languages.

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(2011). Asynchronous Adaptive Optimisation for Generic Data-Parallel Array Programming and Beyond. Arbeitsberichte des Instituts für Wirtschaftsinformatik.

(2011). An interactive visualization tool for the analysis of multi-objective embedded systems design space exploration. Proceedings of the 3rd Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (Rapido ‘11), in conjunction with HiPEAC’11.

(2011). A high-level power model for MPSoC on FPGA. 2011 IEEE IPDPS Workshops & PhD Forum (IPDPSW).

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(2010). VMODEX: A visualization tool for multi-objective design space exploration. Proceedings of the 2010 International Conference on Field-Programmable Technology (FPT’10).

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(2010). Visualization of multi-objective design space exploration for embedded systems. Proceedings of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD’10), Lille, France.

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(2010). The essence of synchronisation in asynchronous data flow programming. Technical Report - Department of Computer Science.

(2010). Single Assignment C: HP^2 programming for heterogeneous concurrent architectures. Intel European Research and Innovation Conference (ERIC’10), Braunschweig, Germany.

(2010). Scenario-based design space exploration of MPSoCs. Proceedings - IEEE International Conference on Computer Design.

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(2010). SaC 1.0 — Single Assignment C — Tutorial. School of Computer Science, University of Hertfordshire.

(2010). S-Net: High-level coordination for the many-core era. Intel European Research and Innovation Conference (ERIC’10), Braunschweig, Germany.

(2010). S-Net language report: Version 2.0. University of Hertfordshire, School of Computer Science.

(2010). S-Net for multi-memory multicores. Declarative Aspects of Multicore Programming, 5th ACM SIGPLAN Workshop (DAMP ‘10).

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(2010). Runtime task mapping based on hardware configuration reuse. Proceedings of the 2010 International Conference on ReConFigurable Computing and FPGAs (ReConFig ‘10), Cancun, Mexico.

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(2010). Resource-agnostic programming for many-core microgrids. (Hand-out) proceedings of the 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), Ischia, Naples, Italy.

(2010). NASA: A generic infrastructure for system-level MP-SoC design space exploration. Proc. of the IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia ‘10).

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(2010). Message driven programming with S-Net: methodology and performance. ICPPW 2010 : proceedings : 2010 39th International Conference on Parallel Processing Workshops.

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(2010). Hardware virtualisation for heterogeneous many-core systems. Intel European Research and Innovation Conference (ERIC’10), Braunschweig, Germany.

(2010). Evaluation of runtime task mapping heuristics with rSesame - a case study. Proceedings - Design, Automation, and Test in Europe conference and exhibition.

(2010). Distributed S-Net: High-level message passing without the hassle. The 1st Workshop on Advances in Message Passing (AMP’10).

(2010). Cluster computing as an assembly process: coordination with S-Net. Cluster, Grid and Cloud Computing, 10th IEEE/ACM International Symposium (CCGrid2010).

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(2010). Asynchronous stream processing with S-Net. International Journal of Parallel Programming.

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(2010). An operational semantics for S-Net. Parallel computing: from multicores and GPU’s to petascale.

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(2010). An adaptive compilation framework for generic data-parallel array programming. Compilers for Parallel Computing, 15th Workshop (CPC 2010).

(2010). An adaptive compilation framework for generic data-parallel array programming. 27. Workshop der GI-Fachgruppe Programmiersprachen und Rechenkonzepte.

(2010). A trace-based scenario database for high-level simulation of multimedia MP-SoCs. Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece.

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(2010). A high-level microprocessor power modeling technique based on event signatures. Journal of Signal Processing Systems for Signal, Image, and Video Technology.

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(2009). Truly nested data-parallelism: compiling SaC for the Microgrid architecture. Draft proceedings of the 21st International Symposium on Implementation and Application of Functional Languages (IFL 2009).

(2009). System-level runtime mapping exploration of reconfigurable architectures. 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS 2009): Rome, Italy, 23-29 May 2009.

(2009). System-level MP-SoC design space exploration using tree visualization. Proceedings of the 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2009), October 15-16 2009, Grenoble, France.

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(2009). Signature-based calibration of analytical performance models for system-level design space exploration. Transactions on High-Performance Embedded Architectures and Compilers.

(2009). S-Net language report: Version 1.0. University of Hertfordshire, School of Computer Science.

(2009). rSesame - A generic system-level runtime simulation framework for reconfigurable architectures. Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT’09): The University of New South Wales, Sydney, Australia, 9-11 December 2009.

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(2009). Introduction. Lecture Notes in Computer Science.

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(2009). Electronic system-level synthesis methodologies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

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(2009). Distributed S-Net: design and implementation. Draft proceedings of the 21st International Symposium on Implementation and Application of Functional Languages (IFL 2009).

(2009). Dependently typed array programs don’t go wrong. The Journal of Logic and Algebraic Programming.

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(2009). Controlling chaos: On safe side-effects in data-parallel operations. DAMP’09: Proceedings of the 4th ACM SIGPLAN Workshop on Declarative Aspects of Multicore Programming: Savannah, Georgia, USA, January 20, 2009.

(2009). Concurrency engineering with S-Net. 15. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS’09): Maria Taferl, 12.-14. Oktober 2009.

(2009). Compiling the functional data-parallel language SaC for Microgrids of Self-Adaptive Virtual Processors. Proceedings of the 14th International Workshop on Compilers for Parallel Computing (CPC’09).

(2008). Towards reconfiguration and self-adaptivity in S-Net. 20th International Symposium on the Implementation and Application of Functional Languages (IFL 2008).

(2008). Descriptor-free representation of arrays with dependent types. 20th International Symposium on the Implementation and Application of Functional Languages (IFL 2008).

(2008). Dependently typed array programs don't go wrong. University of Lübeck, Institute of Software Technology and Programming Languages.

(2008). Daedalus: Toward composable multimedia MP-SoC design. Proceedings of the 45th annual conference on design automation.

(2008). Calibration of abstract performance models for system-level design space exploration. Journal of Signal Processing Systems for Signal, Image, and Video Technology.

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(2007). Towards Multi-application Workload Modeling in Sesame for System-level Design Space Exploration. Proc. of the 7th Int. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII).

(2007). Static Priority Scheduling of Event-Triggered Real-Time Embedded Systems. Formal methods in system design: an international journal.

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(2007). Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration. Proc. of the IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia’07).

(2007). A Framework for Rapid System-level Exploration, Synthesis, and Programming of Multimedia MP-SoCs. Proc. of the ACM/IEEE/IFIP Int. Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS ‘07).

(2006). Special Issue on Architectures, Modeling, and Simulation for Embedded Processors. Journal of Signal Processing Systems for Signal, Image, and Video Technology.

(2006). On the Calibration of Abstract Performance Models for System-level Design Space Exploration. Proc. of the Int. Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (IC-SAMOS 2006).

(2006). A Mixed-level Co-simulation Method for System-level Design Space Exploration. Proc. of the IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia’06).

(2006). A Microthreaded Architecture and its Compiler. Proc. of the Int. Workshop on Compilers for Parallel Computers.

(2004). Static Priority Scheduling of Event-Triggered Real-Time Embedded Systems. Proceedings of the ACM / IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE’04).

(2004). On the Modeling of Intra-task Parallelism in Task-level Parallel Embedded Systems. Domain-Specific Processors: Systems, Architectures, Modeling and Simulation.

(2004). A High-level Programming Paradigm for SystemC. Lecture Notes in Computer Science.

(2004). A High-level Programming Paradigm for SystemC. Proceedings of the Progress Workshop on Embedded Systems.

(2003). Utilizing Synthesis Methods in Accurate Systemlevel Exploration of Heterogeneous Embedded Systems. Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS ' 03).

(2003). IDF Models for Trace Transformtions: A Case Study in Computational Refinement. Proceedings of the 3rd Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS 2003).

(2003). An IDF-based Trace Transformation Method for Communication Refinement. Proceedings of the 40th ACM/IEEE Design Automation Conference (DAC 2003).

(2003). A Software Framework for Efficient Systemlevel Performance Evaluation of Embedded Systems. Proceedings of the 18th ACM Symposium on Applied Computing, Embedded Sytstems track.

(2003). A Multiobjective Optimization Model for Exploring Multiprocessor Mappings of Process Networks. Proceedings of the ACM/IEEE/IFIP Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS ' 03).

(2002). Towards Efficient Design Space Exploration of Heterogenious Embedded Media Systems. Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation.

(2002). Modeling of Intra-task Parallelism in Sesame. Proceedings of the 2nd International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS).

(2002). Modeling Intra-task Parallelism in Task level Parallel Embedded Systems. Proceedings of the Progress workshop on Embedded Systems.

(2001). Towards efficient design space exploration of heterogeneous embedded media systems. Proceeding of the International Workshop on Systems, Architectures, Modeling and Simulation in LNCS.

(2001). Sesame: Simulation of embedded system architectures for multi-level exploration. Proceedings of the conference of the Advanced School for Computing and Imaging (ASCI).

(2001). Non-DMA I/O in Startemis. Informatics Institute.

(2000). Hardware versus Hybrid Data Prefetching in Multimedia Processors: A Case Study. Proceedings of the IEEE International Performance, Computing and Communications Conference.

(1999). TriMedia CPU64 architecture. Proceedings of the IEEE International Conference on Computer Design (ICCD ‘99).

(1999). Evaluation of LH*lh for a multicomputer architecture. Proceedings of the EuroPar ‘99 Conference, distinguished paper.

(1998). Proc. of the 11th int. parallel processing symposium. An architecture workbench for multicomputers.

(1998). Distributed simulation of multicomputer architecture with Mermaid. Proc. of the SCS Symposium on performance evaluation of computer and telecommunications systhems.

(1997). Runtime visualization of computer architecture simulations. Proc. of the 3rd Workshop on Performance Analysis and its Impact on Design (in conjunction with the 24th Int. Symposium on Computer Architecture).

(1997). An architecture workbench for multicomputers. Proc. of the 11th International Parallel Processing Symposium.

(1997). Abstract workload modelling in computer architecture simulation. Proc. of the 3rd Workshop on Performance Analysis and its Impact on Design (in conjunction with the 24th Int. Symposium on Computer Architecture).

(1996). Evaluation of a Mesh of Clos Wormhole Network. Proc. of the 3rd International Conference on High Performance Computing.

(1995). Simulating mimd Multicomputers: the Mermaid approach. IEEE Computer Society TCCA Newsletter.

(1995). Mermaid: modelling and evaluation research in MIMD architecture design. Lecture Notes in Computer Science 919, High Performance Computing and Networking.