Anuj Pathania

Latest

• The paper 'Lifetime Estimation for Core-Failure Resilient Multi-Core Processors' was accepted for IEEE MCSoC '23.
• The paper '3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems' was accepted for publication at IEEE ISVLSI '23.
• The patent 'Power management for multicore processors' has been successfully published under number EP 4 152 124.
• Edge AI
• Thermals
• The chapter 'Pipelined CNN Inference on Heterogeneous Multi-Processor System-on-Chip' was accepted for the book on Embedded Machine Learning for Cyber Physical, IoT, and Edge Computing (Springer).
• The paper 'CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5 D, and 3D Processor-Memory System' was accepted for ACM Transactions on Architecture and Code (TACO).
• HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
• T-TSP
• The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
• CoMeT
• HotSniper
• EnergyLabels
• HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
• The paper 'ChordMap: Automated Mapping of Streaming Applications onto CGRA' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
• ChordMap: Automated Mapping of Streaming Applications onto CGRA
• CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems
• Neural Network-Based Performance Prediction for Task Migration on S-NUCA Many-Cores
• Power-Efficient Heterogeneous Many-Core Design With NCFET Technology
• The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for DATE 2021.